1. Field of the Invention
The present invention relates to charge pump circuits.
2. Description of the Related Art
Semiconductor devices often require a voltage higher than the power supply voltage supplied from a power source circuit integrated within the semiconductor devices. For example, a floating-gate nonvolatile memory device uses a voltage higher than the power supply voltage in data write operations and data erase operations. Such semiconductor storage devices often incorporate a booster circuit for generating the high voltage. The charge pump is one of the most typical booster circuit topologies. A charge pump is provided with a plurality of MOS capacitors and generates a high voltage by using the MOS capacitors, as disclosed in Japanese Laid-Open Patent Application No. JP-A Heisei 9-266281, referred to as the '281 application, hereinafter.
FIG. 1 is a cross sectional diagram showing the structure of a MOS capacitor integrated within a charge pump circuit disclosed in the '281 application. The MOS capacitor TR1 is composed of an NMOS transistor with a triple-well structure. The MOS capacitor TR1 is provided with an N-well 122 formed within a P-type substrate 121, a P-well 124 formed within the N-well 122, N+ regions 126, 127 formed within the P-well 124, and a P+ region 128 also formed within the P-well 124. A gate dielectric 129 is formed on the P-well 124, and a gate electrode 130 is formed on the gate dielectric 129. The gate electrode 130 is connected to a node to be boosted within the charge pump circuit. The N+ regions 126, 127 and the p-well 124 are connected to an input terminal Ts which receives a clock signal CLK. The input terminal Ts may receive an inverted clock signal/CLK, instead of the clock signal CLK.
In using the MOS capacitor TR1, the N-well 122 is biased with the power supply voltage VDD and the P-type substrate 121 is biased with the ground voltage VSS. This effectively suppresses the flow of the pn junction leak current into the MOS capacitor.
The advantage of the MOS capacitor of FIG. 1 is that the capacitance C thereof does not depend on the gate-source voltage Vgs. This allows operating the charge pump circuit on a reduced power supply voltage, effectively improving the efficiency of the charge pump circuit. The reduction in the power supply voltage and the improvement of the efficiency is advantageous for the reduction in the development cost.
One issue of the MOS capacitor TR1 shown in FIG. 1 is the increased parasitic capacitance between the N-well 122 and the P-well 124. As stated above, the N-well 122 is biased with the power supply voltage VDD, while the power supply voltage VDD and the ground voltage VSS are alternately applied to the P-well 124. When the p-well well 124 is pulled up to the power supply voltage VDD, the parasitic capacitance is increased between the N-well 122 and the P-well 124. When the power supply voltage VDD is applied to both of the N-well 122 and the P-well 124, the depletion layer width between the N-well 122 and the P-well 124 is decreased, and thereby the parasitic capacitance therebetween is increased. The increased parasitic capacitance undesirably causes a problem of the increase in the consumption current in the charge pump circuit.